Electrostatic discharge (ESD) is a transient process of high energy transformation from external to internal of an integrated circuit (IC) when the IC is floated. Hundreds or even thousands of volts are transferred during ESD. Such high voltage transformation is a common failure mechanism that is seen on integrated circuit devices. Due to the ever increasing shrinkage in transistor geometries, prevention of ESD damage will become increasingly important.
FIG. 1 is a circuit diagram with ESD protection devices. In FIG. 1, before an input signal is provided into a core circuit 101 via an input pad 102, ESD clamps 104 and 105 are used to bypass an ESD current to the system voltage trace VDD and the ground voltage trace GND, respectively. Similarly, additional ESD clamps 106 and 107 may also be used to bypass an ESD current to the system voltage trace VDD and the ground voltage trace GND, respectively, before an output signal is delivered to the output pad 103. Furthermore, a power clamp 110 may be installed across the VDD and the GND to protect the core circuit 101 against ESD damages.
The grounded-gate n-channel metal-oxide-semiconductor (GGNMOS) transistor has been investigated to serve as an effective ESD protection device. The GGNMOS device is based on snapback mechanism. When the voltage reaches a level beyond the IC normal operation due to ESD zapping, the snapback mechanism enables the GGNMOS to conduct a high level ESD current between its drain and source and subsequently directs the ESD current into the ground. While the ESD zapping occurs, some elementary transistors may firstly turn on, and immediately breakdown with the onset of secondary snapback and the other elementary transistors may be inactive to contribute to the ESD protection. Such phenomenon is referred to as “latch-up”.
The holding voltage of these high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the ICs to be susceptible to the latch-up-like danger in the practical system applications, especially when these devices are used in the ESD power clamp circuit (such as the power clamp 110 of FIG. 1).
Recently, some people have reported to use stacked structures in power clamps. For example, in Proc. EOS/ESD Symposium 2004, Lin et al. have published a new latch up-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure proposed and successfully verified in a 0.25-μm 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latch-up or latch-up-like issues can be avoided by stacked-field-oxide structures for the IC applications with a power supply of 40 V.
FIG. 2 shows another example of a stacked ESD protection device 200. In FIG. 2, the stacked ESD protection device 200 comprises a p-type substrate 201 and a plurality of high-voltage deep n-wells (HVDNWs) 202 formed in the p-type substrate 201. Each of the HVDNWs 202 is isolated from one another. A p-well as an element region 203 is formed in each of the HVDNWs 202. In each element region 203, a pair of separated highly doped n+ regions 205 are formed as drain/source regions. A dielectric layer (not shown) is formed on a channel region between the drain/source regions 205. A conductor 207 as a gate electrode is formed on the dielectric layer. Therefore, an n-channel MOS field-effect transistor (NMOSFET) is formed. Furthermore, a highly doped p+ region 206 in a p-well 204 is provided to connect the p-type substrate 201 to the ground GND. Accordingly, an ESD protection device with stacked NMOSFETs is completed by conducting a current path to connect the NMOSFET ESD protection elements in series.
It is noted that the stacked ESD protection device 200 shown in FIG. 2 with the isolated HVDNWs 202 requires a large layout area. Therefore, there is need in providing a layout area shrink design for high density very-large-scale integration (VLSI) applications.